2012 Symposia on VLSI
Technology & Circuits

VLSI June 12th-15th, Honolulu, Hawaii
VLSI Technology Symposium
June 12-14, 2012
VLSI Circuits Symposium
June 13-15, 2012

The 2012 Symposia on VLSI Technology & Circuits, to be held at the Hilton Hawaiian Village June 12-14, 2012 (Technology) and June 13-15, 2012 (Circuits), are the premier mid-year gatherings for the advancement of microelectronics technology and circuits. They overlap specifically to provide the opportunity for technologists and circuit/system designers to interact and attend presentations by each other in an open forum, offering unique opportunities that are not replicated by other leading conferences. In addition – for the first time – joint technology and circuit focus sessions will be held in 2012.


The following press materials are available for pre-conference publicity for the 2012 VLSI Symposia.


VLSI Symposia 2012 logo (.jpg) (Main PR image)

VLSI Circuit Symposium 2012 logo (.jpg)

VLSI Tech Symposium 2012 logo (.jpg)

Paper C2-1, Components for Generating and Phase Locking 390-GHz7 Signal in 45-nm CMOS (.jpg)

Paper C7-1, A 260 GHz Fully Integrated CMOS Transceiver for Wireless Chip-to-Chip Communication (.jpg)

Paper C17-1, A 25-Gbs/5-mW CMOS/DeSerializer (.jpg)

Paper C8-1, A 0.41μA Standby Leakage 32Kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28nm HKMG CMOS (.jpg)

Paper C9-4, "Brain-Machine Interface"(.pdf)

Paper C9-2, "EEG-Signals acquired with dry electrodes" (.jpg)

Paper C11-1, A 2.8GS/s 44.6mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5GHz in 65nm CMOS (.jpg)

Paper C11-3, A 4.5-mW 8-b 750-MS/s 2-b/Step Asynchronous Subranged SAR ADC in 28-nm CMOS Technology (.jpg)

Paper C12-1, A 22nm Dynamically Adaptive Clock Distribution for Voltage Droop Tolerance (.jpg)

Paper C12-1, A 22nm Dynamically Adaptive Clock Distribution for Voltage Droop Tolerance (.pptx)

Paper C13-1, A 3.1mW/Gbps 30 Gbps Quarter-Rate Triple-Speculation 15-tap SC-DFE RX Data Path in 32nm CMOS (.ppt)

Paper C14-4, 1Gsearch/sec Ternary Content Addressable Memory Compiler with Silicon-Aware Early-Predict Late-Correct Single-Ended Sensing (.jpg)

Paper C16-2, A New 3-bit Programming Algorithm using SLC-to-TLC Migration for 8MB/s High Performance TLC NAND Flash Memory (.jpg)

Paper C18-2, A 69mW 140-meter/60fps and 60-meter/300fps Intelligent Vision SoC for Versatile Automotive Applications v.1 (.jpg)

Paper C18-2, A 69mW 140-meter/60fps and 60-meter/300fps Intelligent Vision SoC for Versatile Automotive Applications v.2 (.jpg)

Paper C23-3, "Integration of solar cells and power electronics" (.jpg)

Paper T4-2, A Novel Low Resistance Gate Fill for Extreme Gate Length Scaling at 20nm and Beyond for Gate-Last High-k/Metal Gate CMOS Technology (.jpg)

Paper T5-1, Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes (.jpg)

Paper T13-5, Strain Engineered Extremely Thin SOI (ETSOI) for High-Performance CMOS (.jpg)

Paper T15-1, High Performance Bulk Planar 20-nm CMOS Technology for Low Power Mobile Applications (.jpg)

Paper T15-2, A 22nm High-Performance and Low-Power CMOS Technology Featuring Fully Depleted Tri-Gate Transistors, Self-Aligned Contacts and High-Density MIM Capacitors v.1 (.jpg)

Paper T19-1, High Mobility Ge pMOSFETs with 0.7nm Ultrathin EOT HfO2/Al2O3/GeOx/Ge Gate Stacks Fabricated by Plasma Post Oxidation (.jpg)

Paper T20-1, Ultrafast Parallel Reconfiguration of 3D-Stacked Reconfigurable Spin Logic Chip with On-chip SPRAM (SPin-transfer torque RAM) (.jpg)

Paper T21-1, Sub-60nm Deeply Scaled Channel Length Extremely-Thin Body InxGa1-xAs-On-Insulator MOSFETs on Si with N-InGaAs Metal S/D and MOS Interface Buffer Engineering (.jpg)


Registration at the VLSI Symposia 2012 is complimentary for the press. Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact one of us for the additional information or interviews you may need.

For registration and other conference information, the 2012 VLSI Symposia home page is: www.vlsisymposium.org/index.html

If you plan to attend, please contact us; or print out the registration page with your contact information, write "Press" on it, and fax or mail it to Conference Manager Phyllis Mahoney, 19803 Laurel Valley Place, Montgomery Village, MD 20886, USA; tel. +1-301-527-0900, ext. 2; fax +1 527-0994. Phyllis also can be reached by email with any registration/attendance questions at phyllism@widerkehr.com.

Be prepared to show a business card when you arrive at the VLSI Symposia.

Editor Contact

Chris Burke
co-Media Relations Director
+1 919-872-8172

Gary Dagastine
co-Media Relations Director
+1 518-785-2724

Meagan Spangler
Media Relations Coordinator
+1 919-872-8172

Phyllis Mahoney
Conference Manager
+1 301-527-0900